This invention relates, generally, to digital circuits and, in particular, to bistable circuits and their application in arbitration circuits.
Digital circuitry finds a variety of uses in digital computers and digital systems. Digital circuits which can be defined in one of two logic states can be used to indicate system-level-states, such as the occurrence/non-occurrence of an event, or the busy/ready status of a resource.
In asynchronous systems, various sub-systems must interact at times, e.g., a request for access to a bus or a memory access, and a decision as to which subsystem request occurs first or should be given priority must be made. To avoid system failures it is essential that the correct decision be made consistently and reliably. An error in the decision may result in allowing two peripheral units simultaneous access to a memory or simultaneous access to a system bus. Bistable circuits, used to indicate the system-level-status, must be in a definable logic state when they are interrogated in order to make a correct decision and to ensure reliable system operation.
In asynchronous systems, two asynchronous input signals occurring at the same time may result in a conflict, in which one signal is trying to set a bistable circuit and at the same time the other signal is trying to reset the bistable circuit. Another conflicting situation can occur when the two asynchronous input signals arrive at a gate simultaneously, one signal trying to pass through the gate and the other signal trying to inhibit the gate, resulting in a small pulse output, sometimes called a runt pulse. A pulse of this nature attempting to set a bistable circuit may not possess sufficient energy to effect the normal switching process of a bistable circuit. In such case, there is a finite probability that the bistable circuit switching may be slowed or delayed, or may oscillate in a metastable state. A metastable state is a state in which the device is indeterminate and may be oscillatory and has not reached the 1 or 0 logic state in a fixed time, the time generally being a normal time designed for the device.
In asynchronous system, synchronization techniques are implemented in an attempt to avoid erroneous decisions which can result in the problems mentioned above, mainly two sub-systems given access to a bus or allowed access to a memory sub-system. Present methods of synchronization utilize synchronizer circuits or networks consisting of a Schmitt trigger circuit with inertial delay elements, the inertial delay elements generally are discrete resistive and capacitive components, the capacitors being of significant value. A number of devices have attempted to minimize and/or eliminate the aforementioned problems. One particular device of interest is disclosed in U.S. Pat. No. 4,093,878 entitled "De-Glitchable Non-Metastable Flip-Flop Circuit". The circuit of the reference patent is comprised of a NAND gate and a Schmitt trigger NAND gate, which have the outputs cross-coupled back to each other's input in the standard configuration for forming a latch circuit. The junction of an RC integrator network is connected to an input of the latch circuit. The RC network tends to make the latch immune to small input signals and also immune to noise signals. The capacitor used in the RC network is of significant size. Another device of interest is disclosed in U.S. Pat. No. 3,983,496 entitled "Pulse Circuit". The circuit disclosed in this patent comprises a Schmitt trigger stage connected to a second stage to form a bistable feedback loop. An RC network is connected to the input of the Schmitt trigger circuit. The RC network in combination with an input gate acts as a pulse stretcher where short pulses are expected to be applied to the input terminal of the pulse circuit.
The circuit of the present invention is designed to eliminate the probability of entering a metastable state and is implemented using components available to LSI integrated circuit technology, which precludes the use of capacitors of any significant value.